Liquid crystal display panel and liquid crystal display array substrate

ABSTRACT

A liquid crystal display panel and liquid crystal display array substrate are disclosed herein. The liquid crystal display array substrate includes scan lines, data lines, first rows of pixel units, and second rows of pixel units. The first rows of pixel units and the second rows of pixel units are arranged alternately. Each of the first rows of pixel units has first pixel structures disposed in a row direction and electrically connected to the scan lines and the data lines, respectively. Each of the second rows of pixel units has second pixel structures disposed along the row direction and electrically connected to the scan lines and the data lines, respectively. The first capacitance value of the first storage capacitor of each first pixel structure is greater than the second capacitance value of the second storage capacitor of each second pixel structure.

RELATED APPLICATIONS

This application claims priority to Taiwan Application Serial Number099146392, filed Dec. 28, 2010, which is herein incorporated byreference.

BACKGROUND

1. Technical Field

The present disclosure relates to display devices, and moreparticularly, liquid crystal display panels and liquid crystal displayarray substrates.

2. Description of Related Art

Liquid crystal displays (LCDs) are more energy efficient and offer saferdisposal than cathode ray tube displays (CRTs). Its low electrical powerconsumption enables it to be used in battery-powered electronicequipment. It is an electronically modulated optical device made up ofany number of pixels filled with liquid crystals and arrayed in front ofa light source (backlight) or reflector to produce images in color ormonochrome.

For LCDs, two dot horizontal inversion (2H inversion) driving isdesigned to circumvent the display flicker problem that results form adot inversion under a dot mask. Significantly, a gate delay results inan undercharge for a high-resolution panel, so a gate must be turned onbefore the input of data. A large difference of charging state of pixelsoccurs due to whether polarity conversion is performed on data lines.Therefore, mesh lines or bright/dark lines may occur because of theundercharge.

In view of the foregoing, there is an urgent need in the related fieldto provide a way to solve or circumvent the problem of the mesh lines orthe bright/dark lines.

SUMMARY

The following presents a simplified summary of the disclosure in orderto provide a basic understanding to the reader. This summary is not anextensive overview of the disclosure and it does not identifykey/critical elements of the present invention or delineate the scope ofthe present invention. Its sole purpose is to present some conceptsdisclosed herein in a simplified form as a prelude to the more detaileddescription that is presented later.

In one or more various aspects, the present disclosure is directed toliquid crystal display panels and liquid crystal display arraysubstrates.

According to one embodiment of the present invention, a liquid crystaldisplay panel includes a first substrate, a second substrate, a liquidcrystal layer, a plurality of scan lines, a plurality of data lines, aplurality of first rows of pixel units and a plurality of second rows ofpixel units. The scan lines are disposed on the first substrate. Thedata lines are disposed on the first substrate and interlaced with thescan lines. The first rows of pixel units are parallel and disposed onthe first substrate. Each of the first rows of the pixel units has aplurality of first pixel structures arranged in a row direction andelectrically connected to the scan lines and the data linesrespectively. Each of the first pixel structures has a first storagecapacitor, and the first storage capacitor has a first capacitancevalue. The second rows of pixel units are parallel and disposed on thefirst substrate. The second rows of the pixel units and the first rowsof the pixel units are arranged alternately. Each of the second rows ofthe pixel units has a plurality of second pixel structures arranged inthe row direction and electrically connected to the scan lines and thedata lines respectively. Each of the second pixel structures has asecond storage capacitor, and the second storage capacitor has a secondcapacitance value, wherein the second capacitance value is less than thefirst capacitance value. The second substrate is disposed opposite tothe first substrate. The liquid crystal layer is disposed between thefirst substrate and the second substrate.

According to a further embodiment of the present invention, a liquidcrystal display array substrate includes a substrate, a plurality ofscan lines, a plurality of data lines, a plurality of first rows ofpixel units and a plurality of second rows of pixel units. The scanlines are disposed on the substrate. The data lines are disposed on thesubstrate and interlaced with the scan lines. The first rows of pixelunits are parallel and disposed on the substrate. Each of the first rowsof the pixel units has a plurality of first pixel structures arranged ina row direction and electrically connected to the scan lines and thedata lines respectively. Each of the first pixel structures has a firststorage capacitor, and the first storage capacitor has a firstcapacitance value. The second rows of pixel units are parallel anddisposed on the substrate. The second rows of the pixel units and thefirst rows of the pixel units are arranged alternately. Each of thesecond rows of the pixel units has a plurality of second pixelstructures arranged in the row direction and electrically connected tothe scan lines and the data lines respectively. Each of the second pixelstructures has a second storage capacitor, and the second storagecapacitor has a second capacitance value, wherein the second capacitancevalue is less than the first capacitance value.

According to another embodiment of the present invention, a liquidcrystal display panel includes a first substrate, a second substrate, aliquid crystal layer, a plurality of first scan lines, a plurality ofsecond scan lines, a plurality of data lines, a plurality of firstcolumns of pixel units and a plurality of second columns of pixel units.The first scan lines and the second scan lines are parallel and disposedon the first substrate alternately. The data lines are disposed on thefirst substrate and interlaced with the scan lines. The first columns ofpixel units are parallel and disposed on the first substrate. Each ofthe first columns of the pixel units has a plurality of first pixelstructures arranged in a column direction and electrically connected tothe first scan lines and the data lines respectively. Each of the firstpixel structures has a first storage capacitor, and the first storagecapacitor has a first capacitance value. The second columns of pixelunits being parallel and disposed on the first substrate. The secondcolumns of the pixel units and the first columns of the pixel units arearranged alternately. Each of the second columns of the pixel units hasa plurality of second pixel structures arranged in the column directionand electrically connected to the second scan lines and the data linesrespectively. Each of the second pixel structures has a second storagecapacitor, and the second storage capacitor has a second capacitancevalue. The second capacitance value is less than the first capacitancevalue. The second substrate is disposed opposite to the first substrate.The liquid crystal layer is disposed between the first substrate and thesecond substrate.

According to yet another embodiment of the present invention, a liquidcrystal display array substrate includes a substrate, a plurality offirst scan lines, a plurality of second scan lines, a plurality of datalines, a plurality of first columns of pixel units and a plurality ofsecond columns of the pixel units. The first scan lines and the secondscan lines are parallel and disposed on the substrate alternately. Thedata lines are disposed on the substrate and interlaced with the scanlines. The first columns of pixel units are parallel and disposed on thesubstrate. Each of the first columns of the pixel units has a pluralityof first pixel structures arranged in a column direction andelectrically connected to the first scan lines and the data linesrespectively. Each of the first pixel structures has a first storagecapacitor, and the first storage capacitor has a first capacitancevalue. The second columns of the pixel units are parallel and disposedon the substrate. The second columns of the pixel units and the firstcolumns of the pixel units are arranged alternately. Each of the secondcolumns of the pixel units has a plurality of second pixel structuresarranged in the column direction and electrically connected to thesecond scan lines and the data lines respectively. Each of the secondpixel structures has a second storage capacitor, and the second storagecapacitor has a second capacitance value, wherein the second capacitancevalue is less than the first capacitance value.

According to still yet another embodiment of the present invention, aliquid crystal display panel includes a first substrate, a secondsubstrate, a liquid crystal layer, a plurality of first scan lines, aplurality of second scan lines, a plurality of data lines, a pluralityof first columns of the pixel units and a plurality of second columns ofthe pixel units. The first scan lines and the second scan lines areparallel and disposed on the first substrate alternately. The data linesare disposed on the first substrate and interlaced with the scan lines.The first columns of the pixel units are parallel and disposed on thefirst substrate. Each of the first columns of the pixel units has aplurality of first pixel structures arranged in a column direction andelectrically connected to the second scan lines and the data linesrespectively. Each of the first pixel structures has a first storagecapacitor, and the first storage capacitor has a first capacitancevalue. The second columns of the pixel units are parallel and disposedon the first substrate. The second columns of the pixel units and thefirst columns of the pixel units are arranged alternately. Each of thesecond columns of the pixel units has a plurality of second pixelstructures arranged in the column direction and electrically connectedto the first scan lines and the data lines respectively. Each of thesecond pixel structures has a second storage capacitor, and the secondstorage capacitor has a second capacitance value. The second capacitancevalue is less than the first capacitance value. The second substrate isdisposed opposite to the first substrate. The liquid crystal layer isdisposed between the first substrate and the second substrate.

According to yet still another embodiment of the present invention, aliquid crystal display array substrate includes a substrate, a pluralityof first scan lines, a plurality of second scan lines, a plurality offirst columns of the pixel units and a plurality of second columns ofthe pixel units. The first scan lines and the second scan lines areparallel and disposed on the substrate alternately. The data lines aredisposed on the substrate and interlaced with the scan lines. The firstcolumns of the pixel units are parallel and disposed on the substrate.Each of the first columns of the pixel units has a plurality of firstpixel structures arranged in a column direction and electricallyconnected to the second scan lines and the data lines respectively. Eachof the first pixel structures has a first storage capacitor, and thefirst storage capacitor has a first capacitance value. The secondcolumns of the pixel units are parallel and disposed on the substrate.The second columns of the pixel units and the first columns of the pixelunits are arranged alternately. Each of the second columns of the pixelunits has a plurality of second pixel structures arranged in the columndirection and electrically connected to the first scan lines and thedata lines respectively. Each of the second pixel structures has asecond storage capacitor, and the second storage capacitor has a secondcapacitance value, wherein the second capacitance value is less than thefirst capacitance value.

Technical advantages are generally achieved, by embodiments of thepresent invention, as follows:

1. The second capacitance value is less than the first capacitancevalue, so that holding voltages of two adjacent pixels are approximatelyor essentially equal after a feed-through voltage drop, thereby solvingthe problem of the mesh lines; and

2. The problem of the mesh lines or the bright/dark lines can becircumvented when the two holding voltages are approximately oressentially equal.

Many of the attendant features will be more readily appreciated, as thesame becomes better understood by reference to the following detaileddescription considered in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The present description will be better understood from the followingdetailed description read in light of the accompanying drawing, wherein:

FIG. 1 is a schematic diagram of a liquid crystal display panelaccording to one embodiment of the present disclosure;

FIG. 2 is a partial circuit diagram of a pixel array of FIG. 1 accordingto one embodiment of the present disclosure;

FIG. 3 is a layout drawing of two adjacent pixel structures of FIG. 2;

FIG. 4 illustrates the pixel array of FIG. 2 with 2H inversion driving;

FIG. 5 shows a display result when the pixel array of FIG. 4 is drivenby the 2H inversion driving;

FIG. 6A a timing diagram illustrating the pixel array of FIG. 2 drivenby the 2H inversion driving according to one embodiment of the presentdisclosure;

FIG. 6B a timing diagram illustrating a pixel array driven by the 2Hinversion driving according to one control experiment;

FIG. 7A a timing diagram illustrating the pixel array of FIG. 2 drivenby the 2H inversion driving according to another embodiment of thepresent disclosure;

FIG. 7B a timing diagram illustrating a pixel array driven by the 2Hinversion driving according to one control experiment;

FIG. 8 illustrates the pixel array of FIG. 1 with 3H inversion drivingaccording to a further embodiment of the present disclosure;

FIG. 9 shows a display result when the pixel array of FIG. 8 is drivenby the 3H inversion driving;

FIG. 10 is a partial circuit diagram of a pixel array of FIG. 1 with the2H inversion driving according to another embodiment of the presentdisclosure;

FIG. 11 shows a display result of a 2V inversion when the pixel array ofFIG. 10 is driven by the 2H inversion driving;

FIG. 12 is a partial circuit diagram of a pixel array of FIG. 1 with(2H+1) inversion driving according to yet another embodiment of thepresent disclosure; and

FIG. 13 shows a display result of a dot inversion when the pixel arrayof FIG. 12 is driven by the (2H+1) inversion driving.

DETAILED DESCRIPTION

In the following detailed description, for purposes of explanation,numerous specific details are set forth in order to attain a thoroughunderstanding of the disclosed embodiments. It will be apparent,however, that one or more embodiments may be practiced without thesespecific details. In other instances, well-known structures and devicesare schematically shown in order to simplify the drawing.

As used in the description herein and throughout the claims that follow,the meaning of “a”, “an”, and “the” includes reference to the pluralunless the context clearly dictates otherwise. Also, as used in thedescription herein and throughout the claims that follow, the terms“comprise or comprising”, “include or including”, “have or having”,“contain or containing” and the like are to be understood to beopen-ended, i.e., to mean including but not limited to. As used in thedescription herein and throughout the claims that follow, the meaning of“in” includes “in” and “on” unless the context clearly dictatesotherwise.

As used herein, “around”, “about” or “approximately” shall generallymean within 20 percent, preferably within 10 percent, and morepreferably within 5 percent of a given value or range. Numericalquantities given herein are approximate, meaning that the term “around”,“about” or “approximately” can be inferred if not expressly stated.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the embodiments. As usedherein, the term “and/or” includes any and all combinations of one ormore of the associated listed items.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which example embodiments belong. Itwill be further understood that terms, such as those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

FIG. 1 is a schematic diagram of a liquid crystal display panel 100according to one embodiment of the present disclosure. As shown in FIG.1, the liquid crystal display panel 100 includes a first substrate 110,a second substrate 120, a liquid crystal layer 130 and a pixel array200.

The second substrate 120 is disposed opposite to the first substrate110. The liquid crystal layer 130 is disposed between the firstsubstrate 110 and the second substrate 120. The pixel array 200 isdisposed on the first substrate 110.

For example, the first substrate 110 is a thin film transistor arraysubstrate, and the second substrate 120 is a color filter substrate.Specifically, the second substrate 120 may include an upper base, apolarization plate, a color filter and common electrodes. For a morecomplete understanding of the pixel array 200 on the first substrate110, herewith embodiments of the present invention are illustrated byreference to the following description considered in FIGS. 2-13.

FIG. 2 is a partial circuit diagram of the pixel array 200 according toone embodiment of the present disclosure. As shown in FIG. 2, the pixelarray 200 includes scan lines 202-208, data lines 212-216, first rows ofpixel units 220 and 240, and second rows of pixel units 230 and 250.These lines and units are disposed on the first substrate 110 of FIG. 1.

The data lines 212-216 are interlaced with the scan lines 202-208. Thefirst rows of pixel units 220, and the second rows of pixel units 230are parallel and disposed on the first substrate 110. The second rows ofpixel units 230 and the first rows of pixel units 220 are arrangedalternately.

Each of the first rows of the pixel units 220 has a plurality of firstpixel structures 222 arranged in a row direction and electricallyconnected to the scan lines 202 and 206 and the data lines 212 and 214respectively. Each of the first pixel structures 222 has a first storagecapacitor 312, and the first storage capacitor 312 has a firstcapacitance value. Each of the second rows of the pixel units 230 has aplurality of second pixel structures 232 arranged in the row directionand electrically connected to the scan lines 204 and 208, and the datalines 212 and 214 respectively. Each of the second pixel structures 232has a second storage capacitor 322, and the second storage capacitor 322has a to second capacitance value. The second capacitance value is lessthan the first capacitance value.

As to the structural difference between the first storage capacitor 312and the second storage capacitor 322, for example, an area of the secondstorage capacitor 322 is smaller than an area of the first storagecapacitor 312; alternatively, a thickness of the second storagecapacitor 322 is greater than a thickness of the first storage capacitor312; alternatively, a dielectric constant the second storage capacitor322 is less than a dielectric constant of the first storage capacitor312. Through any of above options, the second capacitance value is lessthan the first capacitance value. In this embodiment, the areas of thefirst and second storage capacitors are different.

In addition, each of the first pixel structures 222 includes a firstthin film transistor 314. Each of the first thin film transistors 314 isconnected to one of the scan lines 202 and 206, one of the data lines212 and 214, and the first storage capacitor 312. Each of the secondpixel structures 232 includes a second thin film transistor 324. Each ofthe second thin film transistors 324 is connected to one of the scanlines 204 and 208, one of the data lines 212 and 214, and the secondstorage capacitor 322.

Moreover, each of the first pixel structures 222 includes a first liquidcrystal capacitor 316, and the first liquid crystal capacitor 316 isconnected to the first thin film transistor 314; each of the secondpixel structures 232 includes a second liquid crystal capacitor 326, andthe second liquid crystal capacitor 326 is connected to the second thinfilm transistor 324. The other similar pixel structures may be deducedby analogy as above embodiments and, thus, are not repeated herein.

FIG. 3 is a layout drawing of two adjacent pixel structures 232 of FIG.2. As shown in FIG. 3, the second thin film transistor 324 is connectedto the pixel electrode 328, and the pixel electrode 328 can serves asone electrode plate of the second storage capacitor 322. Moreover, thefirst thin film transistor is also connected to the pixel electrode (notshown), and this pixel electrode can serves as one electrode plate ofthe first storage capacitor. In use, the polarity difference between twopixel electrodes 328 introduces fringe electric field, so that liquidcrystal molecules of the liquid crystal layer 130 as shown in FIG. 1 maybe rotated in an unwished direction.

FIG. 4 illustrates the pixel array 220 of FIG. 2 with two dot horizontalinversion (2H inversion) driving. In the 2H inversion driving, forexample, a data driving circuit can provide a pixel data signal 402 forthe data line 212. The pixel data signal 402 represents a gray level ofR, G or B. During the pixel data signal 402 at a high level, a scandriving circuit can provide a scanning signal 412 for the scan line 202to turn on the first thin film transistor 314, so that the first storagecapacitor 312 can be charged. Then, the scan driving circuit can providea scanning signal 414 for the scan line 204 to turn on the second thinfilm transistor 324, so that the second storage capacitor 322 can becharged. The scanning manner for other similar pixel structures may bededuced by analogy as above embodiments and, thus, are not repeatedherein.

Moreover, a common voltage is provided for the common electrode, and theelectrical field is generated between the common electrode and the pixelelectrode, so that the liquid crystal molecules can rotate for renderinga specific gray scale. During the pixel data signal 402 at a low level,the scan driving circuit can provide scanning signals 416 and 418 forthe scan lines 206 and 208 respectively, but the corresponding first andsecond storage capacitor are not charged. The scanning manner for othersimilar pixel structures may be deduced by analogy as above embodimentsand, thus, are not repeated herein.

In general, the pixel data signal has either positive polarity ornegative polarity depending on whether the voltage of the pixel datasignal is higher or lower than the common voltage. A pixel data signalhas positive polarity when its voltage level is higher than the commonvoltage. Likewise, a pixel data signal has negative polarity when itsvoltage is lower than the common voltage. FIG. 5 shows a display resultwhen the pixel array 200 of FIG. 4 is driven by the 2H inversiondriving. As shown in FIG. 5, “+” represents positive polarity, and “−”represents negative polarity. A portion of FIG. 5 indicated by the thickframe is corresponding to the pixel array of FIG. 4.

FIG. 6A a timing diagram illustrating the pixel array 200 of FIG. 2driven by the 2H inversion driving at the level 0 of the grayscaleaccording to one embodiment of the present disclosure. In FIG. 6A,twisted nematic liquid crystal is utilized for example. The secondcapacitance value (0.207 pico-Faraday (pF)) of the second storagecapacitor 322 is less than the first capacitance value (0.247 pF) of thefirst storage capacitor 312. The pixel data signal 402 represents thelevel 0 of the grayscale. Because the scanning signal 412 is earlierthan the pixel data signal 402, the pixel data signal 402 cannottransmitted to the first storage capacitor 312 when first thin filmtransistor 314 is turned on in the beginning. Therefore, the secondcapacitance value (0.207 pF) of the second storage capacitor 322 is lessthan the first capacitance value (0.247 pF) of the first storagecapacitor 312, so that the holding voltage 601 of the first storagecapacitor 312 is equal to the holding voltage 602 of the second storagecapacitor 322 and is 11.055V, thereby solving the problem of the meshlines.

FIG. 6B a timing diagram illustrating a pixel array driven by the 2Hinversion driving at the level 0 of the grayscale according to onecontrol experiment. The parameters and hardware architecture in thecontrol experiment is essentially the same as those in the aboveembodiment of FIG. 6A, except that the second capacitance value (0.247pF) of the second storage capacitor 322 is equal to the firstcapacitance value (0.247 pF) of the first storage capacitor 312. Becausethe first and second capacitance values are equal, the holding voltage603 of the first storage capacitor 312 is 11.055V and the holdingvoltage 604 of the second storage capacitor 322 and is 11.153V. There isa large voltage difference (ΔV=0.098 V) between the holding voltages 603and 604, and thus the problem of the mesh lines occurs.

FIG. 7A a timing diagram illustrating the pixel array 200 of FIG. 2driven by the 2H inversion driving at the level 32 of the grayscaleaccording to one embodiment of the present disclosure. In FIG. 7A, thesecond capacitance value (0.207 pF) of the second storage capacitor 322is less than the first capacitance value (0.247 pF) of the first storagecapacitor 312. The pixel data signal 402 represents the level 32 of thegrayscale. Because the scanning signal 412 is earlier than the pixeldata signal 402, the pixel data signal 402 cannot transmitted to thefirst storage capacitor 312 when first thin film transistor 314 isturned on in the beginning. Therefore, the second capacitance value(0.207 pF) of the second storage capacitor 322 is less than the firstcapacitance value (0.247 pF) of the first storage capacitor 312, so thatthe holding voltage 605 of the first storage capacitor 312 is 10.094Vand the holding voltage 606 of the second storage capacitor 322 and is10.127V. There is a small voltage difference (ΔV=0.033 V) between theholding voltages 605 and 606, and thus the problem of the mesh lines issolved.

FIG. 7B a timing diagram illustrating a pixel array driven by the 2Hinversion driving at the level 32 of the grayscale according to onecontrol experiment. The parameters and hardware architecture in thecontrol experiment is essentially the same as those in the aboveembodiment of FIG. 7A, except that the second capacitance value (0.247pF) of the second storage capacitor 322 is equal to the firstcapacitance value (0.247 pF) of the first storage capacitor 312 and thepixel data signal 402 represents the level 32 of the grayscale. Becausethe first and second capacitance values are equal, there is a largevoltage difference (ΔV=0.098 V) between the holding voltage 607 of thefirst storage capacitor 312 and the holding voltage 608 of the secondstorage capacitor 322, and thus the problem of the mesh lines occurs.

In practice, the second capacitance value of the second storagecapacitor 322 is less than the first capacitance value of the firststorage capacitor 312, so that the problem of the mesh lines is reduced.Preferably, the second capacitance value is in a range of 30-99.9percentage of the first capacitance value, so that users generallycannot detect the mesh lines. More preferably, the second capacitancevalue is in a range of 50-95 percentage of the first capacitance value,so that the users it is hard for users to find out the mesh lines. Mostpreferably, the second capacitance value is in a range of 70-90percentage of the first capacitance value, so as to eliminate the meshlines effectively.

In view of above, the substrate 110 is combined with the pixel array 200to serve as a liquid crystal display array substrate. The liquid crystaldisplay array substrate includes a substrate 110, a plurality of scanlines 202-208, a plurality of data lines 212-216, a plurality of firstrows of pixel units 220 and a plurality of second rows of pixel units230. The scan lines 202-208 are disposed on the substrate 110. The datalines 212-216 are disposed on the substrate 110 and interlaced with thescan lines 202-208. The first rows of pixel units 220 are parallel anddisposed on the substrate 110, wherein each of the first rows of thepixel units 220 has a plurality of first pixel structures 222 arrangedin a row direction and electrically connected to the scan lines 202 and206 and the data lines 212 and 214 respectively, wherein each of thefirst pixel structures 222 has a first storage capacitor 312, and thefirst storage capacitor 312 has a first capacitance value. The secondrows of pixel units 230 are parallel and disposed on the substrate 110,wherein the second rows of the pixel units 230 and the first rows of thepixel units 220 are arranged alternately, wherein each of the secondrows of the pixel units 230 has a plurality of second pixel structures232 arranged in the row direction and electrically connected to the scanlines 204 and 208 and the data lines 212 and 214 respectively, whereineach of the second pixel structures 232 has a second storage capacitor322, and the second storage capacitor 322 has a second capacitancevalue, wherein the second capacitance value is less than the firstcapacitance value.

FIG. 8 illustrates the pixel array of FIG. 1 with 3H inversion drivingaccording to a further embodiment of the present disclosure. The pixelarray 200 of FIG. 8 is essentially the same as the pixel array 200 ofFIG. 2, except that the row of the pixel units 240 acts as a third rowof the pixel units 240 in FIG. 8. The third row of the pixel units 240may be one or more third rows of the pixel units 240. The third rows ofpixel units 240 are parallel and disposed on the first substrate 110,wherein each of the third rows of the pixel units 240 are disposedbetween an adjacent one of the second rows of the pixel units 230 and anadjacent one of the first rows of the pixel units 220, wherein each ofthe third rows of the pixel units 240 has a plurality of third pixelstructures 242 arranged in the row direction and electrically connectedto the scan line 206 and the data lines respectively, wherein each ofthe third pixel structure has a third storage capacitor 332, and thethird storage capacitor 332 has a third capacitance value, wherein thethird capacitance value is equal to the second capacitance value.

In addition, each of the third pixel structure 242 includes a third thinfilm transistor 324. Each of the third thin film transistors 324 isconnected to the scan line 206, one of the data lines 212 and 214, andthe third storage capacitor 332.

Moreover, each of the third pixel structures 242 includes a third liquidcrystal capacitor 336, and the third liquid crystal capacitor 336 isconnected to the third thin film transistor 334.

In the 3H inversion driving, for example, a data driving circuit canprovide a pixel data signal 802 for the data line 212. The pixel datasignal 802 represents a gray level of R, G or B. During the pixel datasignal 802 at a high level, a scan driving circuit can provide ascanning signal 812 for the scan line 202 to turn on the first thin filmtransistor 314, so that the first storage capacitor 312 can be charged.Next, the scan driving circuit can provide a scanning signal 813 for thescan line 203 to turn on the second thin film transistor 324, so thatthe second storage capacitor 322 can be charged. Then, the scan drivingcircuit can provide a scanning signal 814 for the scan line 204 to turnon the third thin film transistor 334, so that the third storagecapacitor 332 can be charged. The scanning manner for other similarpixel structures may be deduced by analogy as above embodiments and,thus, are not repeated herein. FIG. 9 shows a display result when thepixel array of FIG. 8 is driven by the three dot horizontal inversion(3H inversion) driving. A portion of FIG. 9 encircled by the thick framecorresponds to the pixel array of FIG. 8. The present invention can beapplied to nH inversion driving likewise, where n is a positive integer.

FIG. 10 is a partial circuit diagram of a pixel array 200 of FIG. 1 withthe 2H inversion driving according to another embodiment of the presentdisclosure. In FIG. 10, the pixel array 200 is arranged as a 2G1Dstructure, i.e. two gate lines-one data line structure. The pixel array200 includes a plurality of first scan lines 902 and 904, a plurality ofsecond scan lines 903 and 905, a plurality of data lines 912 and 914, aplurality of first columns of pixel units 920 and a plurality of secondcolumns of the pixel units 930. These lines and units are disposed onthe first substrate 110 of FIG. 1.

The first scan lines 902 and 904 and the second scan lines 903 and 905are parallel and disposed on the substrate 110 alternately. The datalines 912 and 914 are disposed on the substrate 110 and interlaced withthe scan lines 902-905. The first columns of pixel units 920 areparallel and disposed on the substrate 110; the second columns of thepixel units 930 are parallel and disposed on the substrate 110. Thesecond columns of the pixel units 930 and the first columns of the pixelunits 920 are arranged alternately.

Each of the first columns of the pixel units 920 has a plurality offirst pixel structures 922 arranged in a column direction andelectrically connected to the first scan lines 902 and 904 and the dataline 912 respectively, wherein each of the first pixel structures 922has a first storage capacitor 1012, and the first storage capacitor 1012has a first capacitance value. Each of the second columns of the pixelunits 930 has a plurality of second pixel structures 932 arranged in thecolumn direction and electrically connected to the second scan lines 903and 905 and the data line 912 respectively, wherein each of the secondpixel structures 932 has a second storage capacitor 1022, and the secondstorage capacitor 1022 has a second capacitance value, wherein thesecond capacitance value is less than the first capacitance value.

As to the structural difference between the first storage capacitor 1012and the second storage capacitor 1022, for example, an area of thesecond storage capacitor 1022 is smaller than an area of the firststorage capacitor 1012; alternatively, a thickness of the second storagecapacitor 1022 is greater than a thickness of the first storagecapacitor 1012; alternatively, a dielectric constant the second storagecapacitor 1022 is less than a dielectric constant of the first storagecapacitor 1012. Through any of above options, the second capacitancevalue is less than the first capacitance value.

In addition, each of the first pixel structures 922 includes a firstthin film transistor 1014. The first thin film transistor 1014 isconnected to the first scan line 902 or 904, the data line 912 and thefirst storage capacitor 1012. Each of the second pixel structures 932includes a second thin film transistor 1024. The second thin filmtransistor 1024 is connected to the second scan line 903 or 905, thedata line 912 and the second storage capacitor 1022.

Moreover, each of the first pixel structures 922 includes a first liquidcrystal capacitor 1016, and the first liquid crystal capacitor 1016 isconnected to the first thin film transistor 1014; each of the secondpixel structures 932 includes a second liquid crystal capacitor 1026,and the second liquid crystal capacitor 1026 is connected to the secondthin film transistor 1024.

In the 2H inversion driving, for example, a data driving circuit canprovide a pixel data signal 1300 for the data line 912. The pixel datasignal 1300 represents a gray level of R, G or B. During the pixel datasignal 1300 at a high level 1202, a scan driving circuit can provide ascanning signal 1312 for the scan line 902 to turn on the first thinfilm transistor 1014, so that the first storage capacitor 1012 can becharged. Then, during the pixel data signal 1300 at a low level 1203,the scan driving circuit can provide a scanning signal 1314 for the scanline 903 to turn on the second thin film transistor 1024, so that thesecond storage capacitor 1022 can be charged. The scanning manner forother similar pixel structures may be deduced by analogy as aboveembodiments and, thus, are not repeated herein. FIG. 11 shows a displayresult of a two dot vertical inversion (2V inversion) when the pixelarray 200 of FIG. 10 is driven by the 2H inversion driving. A portion ofFIG. 11 encircled by the thick frame corresponds to the pixel array ofFIG. 10.

FIG. 12 is a partial circuit diagram of a pixel array of FIG. 1 with twodot horizontal plus one (2H+1) inversion driving according to yetanother embodiment of the present disclosure. In FIG. 12, the pixelarray 200 is arranged as a 2G1 D structure. The pixel array 200 includesa plurality of first scan lines 902 and 904, a plurality of second scanlines 903 and 905, a plurality of data lines 912 and 914, a plurality offirst columns of pixel units 920 and a plurality of second columns ofthe pixel units 930. These lines and units are disposed on the firstsubstrate 110 of FIG. 1.

The first scan lines 902 and 904 and the second scan lines 903 and 905are parallel and disposed on the substrate 110 alternately. The datalines 912 and 914 are disposed on the substrate 110 and interlaced withthe scan lines 902-905. The first columns of pixel units 920 areparallel and disposed on the substrate 110; the second columns of thepixel units 930 are parallel and disposed on the substrate 110. Thesecond columns of the pixel units 930 and the first columns of the pixelunits 920 are arranged alternately.

Each of the first columns of the pixel units 920 has a plurality offirst pixel structures 922 arranged in a column direction andelectrically connected to the second scan lines 903 and 905 and the dataline 912 respectively, wherein each of the first pixel structures 922has a first storage capacitor 1012, and the first storage capacitor 1012has a first capacitance value. Each of the second columns of the pixelunits 930 has a plurality of second pixel structures 932 arranged in thecolumn direction and electrically connected to the first scan lines 902and 904 and the data line 912 respectively, wherein each of the secondpixel structures 932 has a second storage capacitor 1022, and the secondstorage capacitor 1022 has a second capacitance value.

In addition, each of the first pixel structures 922 includes a firstthin film transistor 1014. The first thin film transistor 1014 isconnected to the second scan lines 903 or 905, the data line 912 and thefirst storage capacitor 1012. Each of the second pixel structures 932includes a second thin film transistor 1024. The second thin filmtransistor 1024 is connected to the first scan lines 902 or 904, thedata line 912 and the second storage capacitor 1022.

Moreover, each of the first pixel structures 922 includes a first liquidcrystal capacitor 1016, and the first liquid crystal capacitor 1016 isconnected to the first thin film transistor 1014; each of the secondpixel structures 932 includes a second liquid crystal capacitor 1026,and the second liquid crystal capacitor 1026 is connected to the secondthin film transistor 1024.

In the (2H+1) inversion driving, for example, a data driving circuit canprovide a pixel data signal 1100 for the data line 912. The pixel datasignal represents a gray level of R, G or B. During the pixel datasignal 1100 at a high level 1102, a scan driving circuit can provide ascanning signal 1112 for the scan line 902 to turn on the correspondingsecond thin film transistor 1024, so that the second storage capacitor1022 can be charged. Then, during the pixel data signal 1100 at a lowlevel 1103, the scan driving circuit can provide a scanning signal 1114for the scan line 903 to turn on the corresponding first thin filmtransistor 1014, so that the first storage capacitor 1012 can becharged. Then, during the pixel data signal 1100 at a low level 1103,the scan driving circuit can provide a scanning signal 1116 for the scanline 904 to turn on the corresponding first thin film transistor 1024,so that the second storage capacitor 1022 can be charged. During thepixel data signal 1100 at a high level 1104, a scan driving circuit canprovide a scanning signal 1118 for the scan line 905 to turn on thecorresponding first thin film transistor 1014, so that the first storagecapacitor 1012 can be charged. The scanning manner for other similarpixel structures may be deduced by analogy as above embodiments and,thus, are not repeated herein. FIG. 13 shows a display result of a dotinversion when the pixel array of FIG. 12 is driven by the (2H+1)inversion driving. A portion of FIG. 13 encircled by the thick framecorresponds to the pixel array of FIG. 12.

In the 2H or (2H+1) inversion driving, the second capacitance value ofthe second storage capacitor 1022 is less than the first capacitancevalue of the first storage capacitor 1012, so that holding voltages oftwo adjacent pixels are approximately or essentially equal after afeed-through voltage drop, thereby solving the problem of the meshlines. Preferably, the second capacitance value is 30-99.9 percentage ofthe first capacitance value, so that users generally cannot detect themesh lines. More preferably, the second capacitance value is 50-95percentage of the first capacitance value, so that the users it is hardfor users to find out the mesh lines. Most preferably, the secondcapacitance value is 70-90 percentage of the first capacitance value, soas to eliminate the mesh lines effectively.

In view of above, the substrate 110 is combined with the pixel array 200of FIG. 10 or FIG. 12 to serve as a liquid crystal display arraysubstrate. The liquid crystal display array substrate includes asubstrate 110, a plurality of first scan lines 902 and 904, a pluralityof second scan lines 903 and 905, a plurality of data lines 912 and 914,a plurality of first columns of pixel units 920 and a plurality ofsecond columns of the pixel units 930. The first scan lines 902 and 904and the second scan lines 903 and 905 are parallel and disposed on thesubstrate 110 alternately. The data lines 912 and 914 are disposed onthe substrate 110 and interlaced with the scan lines 902-905. The firstcolumns of pixel units 920 are parallel and disposed on the substrate110; the second columns of the pixel units 930 are parallel and disposedon the substrate 110. The second columns of the pixel units 930 and thefirst columns of the pixel units 920 are arranged alternately.

For the 2H inversion driving, each of the first columns of the pixelunits 920 has a plurality of first pixel structures 922 arranged in acolumn direction and electrically connected to the first scan lines 902and 904 and the data line 912 respectively, wherein each of the firstpixel structures 922 has a first storage capacitor 1012, and the firststorage capacitor 1012 has a first capacitance value. Each of the secondcolumns of the pixel units 930 has a plurality of second pixelstructures 932 arranged in the column direction and electricallyconnected to the second scan lines 903 and 905 and the data line 912respectively, wherein each of the second pixel structures 932 has asecond storage capacitor 1022, and the second storage capacitor 1022 hasa second capacitance value, wherein the second capacitance value is lessthan the first capacitance value.

Alternatively, for the (2H+1) inversion driving, each of the firstcolumns of the pixel units 920 has a plurality of first pixel structures922 arranged in a column direction and electrically connected to thesecond scan lines 903 and 905 and the data line 912 respectively,wherein each of the first pixel structures 922 has a first storagecapacitor 1012, and the first storage capacitor 1012 has a firstcapacitance value. Each of the second columns of the pixel units 930 hasa plurality of second pixel structures 932 arranged in the columndirection and electrically connected to the first scan lines 902 and 904and the data line 912 respectively, wherein each of the second pixelstructures 932 has a second storage capacitor 1022, and the secondstorage capacitor 1022 has a second capacitance value.

Accordingly, the present invention provides the second capacitance valueof the second storage capacitor 1022 that is less than the firstcapacitance value of the first storage capacitor 1012, so that holdingvoltages of two adjacent pixels are approximately or essentially equalafter a feed-through voltage drop, thereby solving the problem of themesh lines.

The reader's attention is directed to all papers and documents which arefiled concurrently with his specification and which are open to publicinspection with this specification, and the contents of all such papersand documents are incorporated herein by reference.

All the features disclosed in this specification (including anyaccompanying claims, abstract, and drawings) may be replaced byalternative features serving the same, equivalent or similar purpose,unless expressly stated otherwise. Thus, unless expressly statedotherwise, each feature disclosed is one example only of a genericseries of equivalent or similar features.

What is claimed is:
 1. A liquid crystal display panel comprising: afirst substrate; a plurality of scan lines disposed on the firstsubstrate; a plurality of data lines disposed on the first substrate andinterlaced with the scan lines; a plurality of first rows of pixel unitsbeing parallel and disposed on the first substrate, each of the firstrows of the pixel units having a plurality of first to pixel structuresarranged in a row direction and electrically connected to the scan linesand the data lines respectively, each of the first pixel structureshaving a first storage capacitor, and the first storage capacitor havinga first capacitance value; a plurality of second rows of pixel unitsbeing parallel and disposed on the first substrate, the second rows ofthe pixel units and the first rows of the pixel units being arrangedalternately, each of the second rows of the pixel units having aplurality of second pixel structures arranged in the row direction andelectrically connected to the scan lines and the data linesrespectively, each of the second pixel structures having a secondstorage capacitor, and the second storage capacitor having a secondcapacitance value, wherein the second capacitance value is less than thefirst capacitance value; a second substrate disposed opposite to thefirst substrate; and a liquid crystal layer disposed between the firstsubstrate and the second substrate.
 2. The liquid crystal display panelof claim 1, wherein each of the first pixel structures includes a firstthin film transistor connected to one of the scan lines, one of the datalines and the first storage capacitor, and each of the second pixelstructures includes a second thin film transistor connected to one ofthe scan lines, one of the data lines and the second storage capacitor.3. The liquid crystal display panel of claim 1, wherein the secondcapacitance value is in a range of 30-99.9 percentage of the firstcapacitance value.
 4. The liquid crystal display panel of claim 1,wherein the second capacitance value is in a range of 50-95 percentageof the first capacitance value.
 5. The liquid crystal display panel ofclaim 1, wherein the second capacitance value is in a range of 70-90percentage of the first capacitance value.
 6. The liquid crystal displaypanel of claim 1, wherein an area of the second storage capacitor issmaller than an area of the first storage capacitor.
 7. The liquidcrystal display panel of claim 1, wherein a thickness of the secondstorage capacitor is greater than a thickness of the first storagecapacitor.
 8. The liquid crystal display panel of claim 1, wherein adielectric constant of the second storage capacitor is less than adielectric constant of the first storage capacitor.
 9. The liquidcrystal display panel of claim 1, wherein the liquid crystal displaypanel is driven by 2H inversion driving.
 10. The liquid crystal displaypanel of claim 1, further comprising a plurality of third rows of pixelunits being parallel and disposed on the first substrate, wherein eachof the third rows of the pixel units are disposed between an adjacentone of the second rows of the pixel units and an adjacent one of thefirst rows of the pixel units, wherein each of the third rows of thepixel units has a plurality of third pixel structures arranged in therow direction and electrically connected to the scan lines and the datalines respectively, wherein each of the third pixel structure has athird storage capacitor, and the third storage capacitor has a thirdcapacitance value, wherein the third capacitance value is equal to thesecond capacitance value.
 11. The liquid crystal display panel of claim10, wherein the liquid crystal display panel is driven by 3H inversiondriving.
 12. A liquid crystal display array substrate comprising: asubstrate; a plurality of scan lines disposed on the substrate; aplurality of data lines disposed on the substrate and interlaced withthe scan lines; a plurality of first rows of pixel units being paralleland disposed on the substrate, each of the first rows of the pixel unitshaving a plurality of first pixel structures arranged in a row directionand electrically connected to the scan lines and the data linesrespectively, each of the first pixel structures having a first storagecapacitor, and the first storage capacitor having a first capacitancevalue; and a plurality of second rows of pixel units being parallel anddisposed on the substrate, the second rows of the pixel units and thefirst rows of the pixel units being arranged alternately, each of thesecond rows of the pixel units having a plurality of second pixelstructures arranged in the row direction and electrically connected tothe scan lines and the data lines respectively, each of the second pixelstructures having a second storage capacitor, and the second storagecapacitor having a second capacitance value, wherein the secondcapacitance value is less than the first capacitance value.